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rev. c m112685 dat-31575-sp 070930 page 1 of 12 '. )''#$/&-')#
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product features ? single positive supply voltage, +3v ? immune to latch up ? excellent accuracy, 0.1 db typ ? serial control interface ? low insertion loss ? high ip3, +52 dbm ? very low dc power consumption ? excellent return loss, 20 db typ ? small size 4.0 x 4.0 mm typical applications ? base station infrastructure ? portable wireless ? catv & dbs ? mmds & wireless lan ? wireless local loop ? unii & hiper lan ? power ampli?er distortion canceling loops general description the dat-31575-sp is a 75 7 rf digital step attenuator that offers an attenuation range up to 31.5 db in 0.5 db steps. the control is a 6-bit serial interface, operating on a single +3 volt supply. the dat-31575-sp is produced using a unique cmos process on silicon, offering the performance of gaas, with the advan- tages of conventional cmos devices. digital step attenuator 31.5 db, 0.5 db step 6 bit, serial control interface, single positive supply voltage, +3v 75 7 dc-2000 mhz simpli?ed schematic digital serial control rf input 16db 8db 4db 2db 1db 0.5db rf out dat-31575-sp+ dat-31575-sp + rohs compliant in accordance with eu directive (2002/95/ec) the +suf?x identi?es rohs compliance. see our web site for rohs compliance methodologies and quali?cations.
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rf electrical speci?cations, dc-2000 mhz, t amb =25c, v dd =+3v absolute maximum ratings parameter ratings operating temperature -40c to 85c storage temperature -55c to 100c v dd -0.3v min., 4v max. voltage on any input -0.3v min., v dd +0.3v max. esd, hbm 500v esd, mm 100v input power +24dbm parameter min. typ. max. units v dd , supply voltage 2.7 3 3.3 v i dd , supply current 100 a control input low 0.3xv dd v control input high 0.7xv dd v control current 1 a dc electrical speci?cations parameter min. typ. max. units switching speed, 50% control to 0.5db of attenuation value 1.0 sec switching control frequency 25 khz switching speci?cations 2. input ip3 and 1db compression degrades below 1 mhz parameter freq. range (ghz) min. typ. max. units accuracy @ 0.5 db attenuation setting dc-1.2 0.03 0.17 db 1.2-2.0 0.05 0.18 db accuracy @ 1 db attenuation setting dc-1.2 0.03 0.24 db 1.2-2.0 0.1 0.25 db accuracy @ 2 db attenuation setting dc-1.2 0.07 0.28 db 1.2-2.0 0.15 0.3 db accuracy @ 4 db attenuation setting dc-1.2 0.05 0.36 db 1.2-2.0 0.15 0.4 db accuracy @ 8 db attenuation setting dc-1.2 0.1 0.52 db 1.2-2.0 0.24 0.6 db accuracy @ 16 db attenuation setting dc-1.2 0.23 0.84 db 1.2-2.0 0.8 1.0 db insertion loss (note1) @ all attenuator set to 0db dc-1.2 1.2 1.8 db 1.2-2.0 1.6 2.1 db input ip3 (note2) (at min. and max. attenuation) dc-2.0 +52 dbm input power @ 0.2db compression (note2) (at min. and max. attenuation) dc-2.0 +24 dbm vswr dc-1.2 1.6 2.0 1.2-2.0 1.7 2.0 notes: 1. i. loss values are de-embedded from test board loss (test boards insertion loss: 0.10db @100mhz, 0.40db @1200mhz, 0.55db @2000mhz, 0.75db @4000mhz)
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function pin number description c16 1 control for attenuation bit, 16 db (notes 3,4) rf in 2 rf in port (note 1) data 3 serial interface data input (note 3) clock 4 serial interface clock input le 5 latch enable input (note 2) v dd 6 power supply n/c 7 not connected n/c 8 not connected v dd 9 power supply gnd 10 ground connection gnd 11 ground connection gnd 12 ground connection v dd 13 power supply rf out 14 rf out port (note 1) c8 15 control for attenuation bit, 8 db (note 4) c4 16 control for attenuation bit, 4 db (note 4) c2 17 control for attenuation bit, 2 db (note 4) gnd 18 ground connection c1 19 control for attenuation bit, 1 db (note 4) c0.5 20 control for attenuation bit, 0.5 db (note 4) gnd paddle paddle ground (note 5) notes: 1. both rf ports must be held at 0vdc or dc blocked with an external series capacitor. 2. latch enable (le) has an internal 100k resistor to v dd . 3. place a 10k resistor in series, as close to pin as possible to avoid freq. resonance. 4. refer to power-up control settings. 5. the exposed solder pad on the bottom of the package (see pin con?guration) must be grounded for proper device operation. pin description gnd gnd gnd gnd vdd vdd vdd n/c n/c rfout c8 le clock data rfin c16 c4 c2 c1 c0.5 2x2mm paddle ground 15 14 13 12 11 1 2 3 4 5 6 7 8 9 20 19 18 17 16 10 pin con?guration (top view)
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typical performance curves attenuation (0.5db) @ +25c, +85c, -45c 0 0.2 0.4 0.6 0.8 1 0 500 1000 1500 2000 2500 3000 frequency (mhz) (db) -45c +25c +85c attenuation (1db) @ +25c, +85c, -45c 0.4 0.6 0.8 1 1.2 1.4 0 500 1000 1500 2000 2500 3000 frequency (mhz) (db) -45c +25c +85c attenuation (2db) @ +25c, +85c, -45c 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 0 500 1000 1500 2000 2500 3000 frequency (mhz) (db) -45c +25c +85c attenuation (4db) @ +25c, +85c, -45c 3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 0 500 1000 1500 2000 2500 3000 frequency (mhz) (db) -45c +25c +85c attenuation (8db) @ +25c, +85c, -45c 6.4 6.6 6.8 7 7.2 7.4 7.6 7.8 8 8.2 8.4 8.6 0 500 1000 1500 2000 2500 3000 frequency (mhz) (db) -45c +25c +85c insertion loss (ref) @ +25c, +85c, -45c 0 1 2 3 4 5 6 7 0 500 1000 1500 2000 2500 3000 frequency (mhz) (db) +85c +25c -45c
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typical performance curves attenuation (16db) @ +25c, +85c, -45c 12 12.5 13 13.5 14 14.5 15 15.5 16 16.5 17 0 500 1000 1500 2000 2500 3000 frequency (mhz) (db) -45c +25c +85c return loss in s11 (ref) @ +25c, +85c, -45c 0 10 20 30 40 50 0 500 1000 1500 2000 2500 3000 frequency (mhz) (db) -45c +25c +85c return loss out s22 (ref) @ +25c, +85c, -45c 0 10 20 30 40 50 0 500 1000 1500 2000 2500 3000 frequency (mhz) (db) -45c +25c +85c return loss in s11 (major attenuation steps) @ +25c 0 10 20 30 40 50 0 500 1000 1500 2000 2500 3000 frequency (mhz) (db) att=0db att=0.5db att=1db att=2db att=4db att=8db att=16db att=31.5db return loss out s22 (major attenuation steps) @ +25c 0 10 20 30 40 50 0 500 1000 1500 2000 2500 3000 frequency (mhz) (db) att=0db att=0.5db att=1db att=2db att=4db att=8db att=16db att=31.5db attenuation (31.5db) @ +25c, +85c, -45c 22 23 24 25 26 27 28 29 30 31 32 33 0 500 1000 1500 2000 2500 3000 frequency (mhz) (db) -45c +25c +85c
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typical performance curves ip-3 input (major attenuation steps) @ +25c 0 10 20 30 40 50 60 70 0 200 400 600 800 1000 1200 1400 1600 1800 200 0 frequency (mhz) (dbm) att=0db att=0.5db att=1db att=2db att=4db att=8db att=16db att=31.5db ip-3 input (major attenuation steps) @ +85c 0 10 20 30 40 50 60 70 0 200 400 600 800 1000 1200 1400 1600 1800 2000 frequency (mhz) (dbm) att=0db att=0.5db att=1db att=2db att=4db att=8db att=16db att=31.5db ip-3 input (major attenuation steps) @ -45c 0 10 20 30 40 50 60 70 0 200 400 600 800 1000 1200 1400 1600 1800 2000 frequency (mhz) (dbm) att=0db att=0.5db att=1db att=2db att=4db att=8db att=16db att=31.5db compression @input power=+24dbm (+25c) -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0 200 400 600 800 1000 1200 1400 1600 1800 2000 frequency (mhz) (db) att=0db att=0.5db att=1db att=2db att=4db att=8db att=16db att=31.5db compression @input power=+24dbm (+85c) -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0 200 400 600 800 1000 1200 1400 1600 1800 2000 frequency (mhz) (db) att=0db att=0.5db att=1db att=2db att=4db att=8db att=16db att=31.5db compression @input power=+24dbm(-45c) -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0 200 400 600 800 1000 1200 1400 1600 1800 2000 frequency (mhz) (db) att=0db att=0.5db att=1db att=2db att=4db att=8db att=16db att=31.5db
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outline drawing (dg983-1) device marking

31575 suggested layout, tolerance to be within .002 pcb land pattern outline dimensions ( ) inch mm a bcdefghj k l m n p q r wt. grams .157 .157 .035 .008 .081 .081 .010 .022 .020 .166 .166 .070 .012 .020 .070 .04 4.00 4.00 0.90 0.20 2.06 2.06 0.25 0.56 0.50 4.22 4.22 1.78 0.31 0.51 1.78
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suggested layout for pcb design (pl-186) the suggested layout shows only the footprint area of the dat, and the components located near this area (i.e.: r1-r7). for the complete layout, see photo and schematic diagram on page 11 of 12. notes: 1. trace width is shown for fr4 with dielectric thickness. .025 .002. copper: 1/2 oz. each side. for other materials trace width may need to be modified. 2. 0603 size chip foot prints shown for reference, values of resistors will vary based on application. 3. bottom side of the pcb is continuous ground plane. denotes pcb copper layout with smobc (solder mask over bare copper) denotes copper land pattern free of soldermask
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the serial interface is a 6-bit serial in, parallel-out shift register buffered by a transparent latch. it is controlled by three cmos-compatible signals: data, clock, and latch enable (le). the data and clock inputs allow data to be serially entered into the shift register, a process that is independent of the state of the le input. the le input controls the latch. when le is high, the latch is transparent and the contents of the serial shift register control the attenuator. when le is brought low, data in the shift register is latched. the shift register should be loaded while le is held low to prevent the attenuator value from changing as data is entered. the le input should then be toggled high and brought low again, latching the new data. the timing for this operation is de?ned by figure 1 (serial interface timing diagram) and table 2 (serial interface ac characteristics). simpli?ed schematic figure 1: serial interface timing diagram table 2. serial interface ac characteristics symbol parameter min. max. units f clk serial data clock frequency (note 1) 10 mhz t clkh serial clock high time 30 ns t clkl serial clock low time 30 ns t lesup le set-up time after last clock falling edge 10 ns t lepw le minimum pulse width 30 ns t sdsup serial data set-up time before clock rising edge 10 ns t sdhld serial data hold time after clock falling edge 10 ns note 1. fclk veri?ed during the functional pattern test. serial programming sections of the functional pattern are clocked at 10mhz to verify fclk speci- ?cation. the dat-31575-sp serial interface consists of 6 control bits that select the desired attenuation state, as shown in table 1 : truth table table 1. truth table attenuation state c16 c8 c4 c2 c1 c0.5 reference 0 00000 0.5 (db) 0 00001 1 (db) 0 00010 2 (db) 0 00100 4 (db) 0 01000 8 (db) 0 10000 16 (db) 1 00000 31.5 (db) 1 11111 note: not all 64 possible combinations of c0.5 - c16 are shown in table le clock data msb lsb t lesup t sdsup t sdhld t lepw digital serial control rf input 16db 8db 4db 2db 1db 0.5db rf out
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the dat-31575-sp, uses a common 6-bit serial word format, as shown in table 3 : 6-bit attenuator serial programming register map. the ?rst bit, the msb, corresponds to the 16-db step and the last bit, the lsb, corresponds to the 0.5 db step. the dat-31575-sp always assumes a speci?able attenuation setting on power-up, allowing a known at- tenuation state to be established before an initial serial control word is provided. when the attenuator powers up, the six control bits are set to whatever data is present on the six data inputs (c0.5 to c16). this allows any one of the 64 attenuation settings to be speci?ed as the power-up state. power-up control settings table 3. 6-bit attenuator serial programming register map b5 b4 b3 b2 b1 b0 c16 c8 c4 c2 c1 c0.5 msb (?rst in) lsb (last in)
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tb-344 evaluation board schematic diagram dat c0.5 c1 gnd c2 c4 c16 data clock le v dd v dd gnd c8 v dd gnd r1 r2 r3 r4 r5 r6 r7 ic1 rfin rfout connected to +v dd 64 2 r8 r9 r11 c6 r10 +vcc c1 c2 c3 c4 c5 n/c n/c 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 14 7 1 3 5 8101213 11 9 c l o c k le data gnd d a t a l e c l k gnd n/c 12345 serial control j1 c l o c k le data g nd g n d gnd v dd 1234 dc supply j2 gnd rfin rfout + tb-344 bill of materials r1 - r11 resistor 0603 10 kohm +/- 1% c1 - c5 npo capacitor 0603 100pf +/- 5% c6, c7 tantalum capacitor 100nf +/- 10% ic1 hex inverting schmitt trigger mm74hc14
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tape and reel packaging information table t&r tr no. no. of devices designation letter reel size tape width pitch unit orientation 3000 t 13 inch t-005 multiples of 10, less than full reel of 1k pr 13 inch 12 mm 8 mm multiples of 10, on tape only e not applicable ordering information model no. description packaging designation letter (see table t&r) quantity min. no. of units price $ ea. dat-31575-sp (+) serial interface, single positive voltage e 10 $3.80 tb-344 test board only not applicable 1 $79.95 how to order example: 3000 pieces of dat-31575-sp+ 1k dat-31575-sp+ t&r=t quantity model no. t&r designation letter (see table t&r) direction of feed tape cavity

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